1. Field of the Invention
The present invention is related to power management of computer bus connected devices and, more particularly, to power management of computer bus connected devices by control of a bus clock signal.
2. Description of the Related Art
A bus provides a mechanism for communications between components of a system or microcontroller. A bus is essentially a collection of wires through which data can be transmitted from one point of a system to another part of the system. In a computer system, for example, a bus connects internal components of the computer to the central processing unit (CPU) and to main memory.
A Peripheral Component Interconnect (PCI) local bus is a high performance synchronous bus architecture that interconnects chips, expansion boards, and processor/memory subsystems. A PCI bus implements a multiplexed address and data bus, with all data transfers being performed relative to a PCI bus clock (CLK).
The PCI bus supports initiators (also known as bus masters), which are intelligent devices that can gain control of the PCI bus. PCI bus masters and the CPU can perform tasks independently of each other. In a typical configuration, the CPU is connected to the PCI bus via a host/PCI bridge, frequently referred to as the north bridge or the host bridge. Expansion busses for devices such as Industry Standard Architecture (ISA) or Extended ISA (EISA) devices are typically connected to the PCI bus via a PCI/ISA bridge, frequently referred to as a south bridge. The south bridge is typically implemented as a chip set that incorporates other functions such as an interrupt controller, an IDE controller, and a DMA controller.
By convention, PCI signals that assume a logic low state when asserted are designated by a pound sign (#) at the end of the signal name. For example, the RST# signal is asserted low to reset the PCI bus. Signal names not ending with a pound sign are asserted high.
Each PCI initiator has a pair of arbitration lines that connect it directly to a PCI bus arbiter. Initiators request ownership of the PCI bus by asserting a REQ# (Request) signal to the PCI arbiter, typically located in a host/PCI or PCI/expansion bus chip set. The PCI arbiter grants bus ownership according to a bus fairness protocol by asserting a GNT# (grant) signal to the requesting initiator. When the initiator samples the GNT# signal asserted, the initiator must wait for the completion of any activity by the initiator currently in control of the bus.
Once the initiator owns the PCI bus, transfers occur between the initiator and a target device (or bus slave). Transfers on the PCI bus are burst operations. The PCI bus transfer includes one address phase and one or more data phases. Each cycle begins with the address phase followed by the data phases. The data phases may repeat indefinitely, but each PCI device has its own timer that defines the maximum amount of time that it may own the PCI bus. The timer is set by the CPU as part of the configuration space.
The PCI bus uses various signals, such as system signals and interface control signals. One system signal is for CLK, which provides the timing reference for all transfers on the PCI bus. All PCI signals except reset (RST#) and interrupts are sampled on the rising edge of the CLK signal, and all bus-timing specifications are defined relative to the rising edge. The minimum frequency of the CLK signal is specified at 0 Hz, which allows CLK to be xe2x80x9csuspendedxe2x80x9d to save power.
One interface control signal is the STOP# signal, which is asserted by a target to request the initiator to terminate the current transaction. If a target requires a long period of time to respond to a transaction, it may use the STOP# signal to suspend the transaction so the PCI bus can perform other interim transfers. The target issues a xe2x80x9cRetryxe2x80x9d if STOP# is asserted during the first data phase. No data is transferred during the transactions, and the initiator is required to Retry the transaction later. On the other hand, the target issues a xe2x80x9cDisconnectxe2x80x9d if STOP# is asserted after one or more data phases have successfully completed. For Disconnect, the initiator may choose to continue the transaction at a later time or may choose not to resume the transaction.
Another interface control signal is the DEVSEL# signal, which is asserted by a PCI target when the target detects its own address on the PCI bus. DEVSEL# may be asserted from one to three clocks after the address phase, but must be asserted prior to or with the clock edge in which a target ready (TRDY#) signal is asserted. Once DEVSEL# is asserted, it is deasserted until the last data phase has completed, or the target issues a target abort (i.e., the target asserts STOPS and deasserts DEVSEL# and TRDY#, if not already deasserted). If the initiator does not detect DEVSEL# asserted within six CLK periods, the initiator must assume that the target cannot respond or that the address is unpopulated and terminate the transaction in a master abort.
If a fatal error occurs or the target will never be able to respond to the transaction for some other reason, the target asserts STOP# and deasserts DEVSEL# and TRDY# to signal a target abort to the initiator, indicating an abnormal termination of the bus transfer. A target abort instructs the initiator not to retry the transaction. The initiator can use the target abort to signal system software that a fatal error has occurred.
The initiator uses the FRAME# signal to indicate that the initiator is ready to complete its final data phrase. In addition to the normal termination of a transaction, this may occur when the initiator is preempted by the arbiter deasserting the GNT# signal, or when no target has responded to the address by asserting DEVSEL#. In the latter case, the initiator aborts the transaction and indicates a master abort in the initiator""s configuration register.
The CLKRUN# (clock running) signal is an optional sustained tri-state input/output signal used to facilitate stopping the CLK signal to save power. CLKRUN# is intended for xe2x80x9cmobilexe2x80x9d environments in which reducing power consumption (for example, to extend battery life) is critical; however, CLKRUN# can be used in non-mobile environments to create a system design that draws as little current as possible.
Because most ISA devices do not announce their presence on the bus, configuration software typically cannot detect them and assign address ranges to their address detectors. Therefore, typical ISA bridges use xe2x80x9csubtractive decodingxe2x80x9d techniques. Subtractive decoding means that the ISA bridge will claim (and pass on to the ISA bus) all transactions that fall into the overall ISA memory or I/O space unclaimed by a PCI device. PCI devices must assert DEVSEL# during one of the first three clock cycles immediately following the completion of the address phase. If DEVSEL# is not detected by the subtractive decoder during those three clock cycles, the subtractive decoder asserts DEVSEL# during the fourth clock cycle, and initiates the transaction on the ISA bus. Only one subtractive decoder is allowed on a PCI bus, and is typically the ISA bridge. However, other subtractive decoders are possible.
Clock generation logic (typically part of the PCI chip set) keeps CLKRUN# asserted when the clock is running normally. During periods when the clock has been stopped (or slowed), the clock generation logic monitors CLKRUN#. Asserting CLKRUN# by initiator and target devices requests the PCI clock-signal to be restored to full speed. The clock cannot be stopped if the bus is not idle. Before stopping or slowing the clock frequency, the clock generation logic deasserts CLKRUN# for one clock cycle to inform PCI devices that the clock is about to be stopped (or slowed). After deasserting CLKRUN# for one clock cycle, the clock generation logic tri-states its CLKRUN# output driver. A keeper resistor on CLKRUN# assumes responsibility for maintaining the deasserted state of CLKRUN# during any period in which the clock is stopped (or slowed).
The clock continues to run unchanged for a minimum of four clock cycles after the clock generation logic deasserts CLKRUN#, indicating its intention to stop (or slow) the clock. During this period of time, a target (or master) that requires continued clock operation, for example, to perform internal housekeeping after the completion of a transaction, may reassert CLKRUN# for two PCI clock cycles to request continued generation of CLK. When the clock generation logic samples CLKRUN# reasserted, it reasserts CLKRUN# and continues to generate the clock, rather than stopping it or slowing it down.
After the clock has been stopped (or slowed), a master or multiple masters may require clock restart in order to request use of the PCI bus. Prior to issuing the bus request, therefore, the master(s) must first request clock restart. This is accomplished by asserting CLKRUN#. When the clock generation logic detects CLKRUN# asserted by another party, it turns on (or speeds up) the clock and turns on its CLKRUN# output driver to assert CLKRUN#. When the master detects CLKRUN# asserted for two rising edges of the PCI CLK signal, the master may then tri-state its CLKRUN# output driver.
The architecture described above provides the capability for shutting off the PCI clock signal to all of the PCI devices after a determination that those PCI devices that support having their clocks turned off are in an idle state. The clock signals are turned off only when all of the PCI devices are idle. If one device is transferring data to another device, then all devices will have their clocks running. When the clock is off, the PCI devices typically go into a low-power state. Thus, some potential power savings are not gained because all devices must be idle before turning off any PCI clocks.
A clock control mechanism provides enhanced power management for devices connected to a computer bus. A clock generator generates a clock signal to the bus-connected devices. A clock controller controls the clock generator, signaling it to start and stop the clock. A device clock controller coupled to the clock controller and at least one other bus-connected device signals the clock controller that the bus is idle when all of the other bus-connected devices are idle. If some of the other bus-connected devices are idle, then the device clock controller individually disconnects the clock signal from any of the other bus-connected devices that are idle.
In one embodiment, a clock running signal is deasserted by the clock controller to indicate that the clock signal is about to be stopped. The device clock controller reasserts the clock running signal if any of the other bus-connected devices are active, and individually asserts the clock running signal to each of the other bus-connected devices. Each active device of the other bus-connected devices asserts its individual copy of the clock running signal.
In another embodiment, the clock controller uses a gate to disconnect the clock signal from each of the other bus-connected devices.
In one embodiment, when some of the other bus-connected devices are idle, the device clock controller monitors transactions on the computer bus. Unclaimed transactions are claimed by the device clock controller and a retry of the transaction is forced. The device clock controller then reconnects the clock signal to the other bus-connected devices and signals the clock controller that some of the other bus-connected devices are active. In one embodiment, the device clock controller is a subtractive decoder that reconnects the clock signal to all of the other bus-connected devices. In another embodiment, the device clock controller is a positive decoder and reconnects the clock signal to the other bus-connected device addressed by the transaction.